1. Field of the Invention
The present invention generally relates to a semiconductor device used as a power semiconductor device, e.g., a vertical or lateral MOSFET (metal oxide semiconductor field effect transistor) and a vertical or lateral IGBT (insulated gate bipolar transistor). The semiconductor device of the present invention can suitably be employed for a MOS-IC, etc. as a single unit or with the incorporation of a power semiconductor device.
2. Related Arts
Recently, a vertical type power MOSFET has been used in many industrial fields for various features thereof such as high frequency characteristics, fast switching speed and low power driving. Along with the spread of the vertical power MOSFET, there is an increasing demand for lower loss and lower cost, while the ON-resistance reduction by means of microprocessing and cell shape improvement has reached its limit. For example, a planar type DMOSFET has the minimal point from which the ON-resistance will not decrease even if the unit cell dimension is miniaturized, and it has been known that the major cause of the existence of the minimal point is an increase in the JFET (junction field effect transistor) resistance located between two adjacent body junctions.
Various constructions have been proposed in an attempt to break through this limit. Common to these proposals is a construction in which a groove is formed on an element surface and a channel part (inversion layer formation region) is disposed on a side surface of the groove. By this construction, even if the unit cell dimension is reduced, the consequent increase in the JFET resistance is negligible.
An example of the conventional manufacturing method with the above construction with the channel part on the side surface of the groove has been disclosed in the Japanese Unexamined Patent Publication No. 61-199666, for example, in which the groove is formed by means of RIE (reactive ion etching) and the channel part is formed on the side surface of the formed groove. Here, the RIE is a physical etching technique with a high process controllability and features an excellent anisotropy and a consequent high resistance to side etch due to the acceleration of ionized gas in a constant direction. However, there is a problem with the RIE that as the ionized gas physically collides against the semiconductor device, a lattice defect is inevitably caused in the etched surface; consequently channel mobility is degraded; and as a result, the ON-resistance increases.
As manufacturing methods which can control a lattice defect, there have been disclosed manufacturing methods using wet etching techniques in International Publication No. PCT WO93/03502 and the Japanese Unexamined Patent Publication No. 62-12167, for example. The proposed DMOS structure has a concave or bathtub-shaped groove structure fabricated by a combination of local oxidation of silicon (LOCOS) technique and chemically etching off the formed thick oxide film (hereinafter referred to as a LOCOS oxide film), which obtains the elimination of JFET resistance while suppressing the occurrence of lattice defects by means of the concave configuration thereof to obtain a high channel mobility.